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baab Senior Member Offline Posts: 178 EA	Re: How to choose Rp, L, C for cascode LNA? Reply #15 - Feb 14^th, 2014, 7:36pm Hi, I think in the circuit above, Ls and Lg already form the input matching network and we don't need to make another one like L, T or Pi networks. Is that right?
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RFICDUDE Community Fellow Offline Posts: 323	Re: How to choose Rp, L, C for cascode LNA? Reply #16 - Feb 16^th, 2014, 5:04am Hi Baab, Looks like you did not recalculate or remeasure Cgs after you scaled the width from 24um to 773um to raise gm from 14mS to 442mS. Cgs is proportional to width, so Cgs will increase by a factor of 32.
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baab

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Re: How to choose Rp, L, C for cascode LNA?
Reply #17 - Feb 16^th, 2014, 7:57am

RFICDUDE wrote on Feb 16^th, 2014, 5:04am:

Hi Baab,

Looks like you did not recalculate or remeasure Cgs after you scaled the width from 24um to 773um to raise gm from 14mS to 442mS. Cgs is proportional to width, so Cgs will increase by a factor of 32.

Thanks. However, let's me explain it a bit more.

As in the picture, first I calculated optimum Q for minimum NF.
From Q computed, the total Cgs is determined with the formula:
Cgs = 1/(Omega* Q* 50Ohms)
(Cgs here is the capacitance with minimum NF, after Cgs is calculated I need to resize the width of transistors to get the Cgs value)
And from that Cgs I can figure out the total width of transistors with the formula:

W (final W) = Cgs/(2/3 * Cox* L)

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RFICDUDE

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Re: How to choose Rp, L, C for cascode LNA?
Reply #18 - Feb 16^th, 2014, 11:56am

I guess what was throwing me off is that you have a very large gm for the size of the device, but I missed that you are using a fairly large bias voltage.

My misinterpretation aside ...
The transit frequency is very high and the resulting Ls is unrealistically small to implement.

I have seen papers where Cgs is intentionally made bigger without increasing transistor area by simply placing some additional fixed capacitance across Cgs. This lowers the transit frequency independent of gm and gives you a degree of freedom to use more practical values of Ls for the gate impedance match problem.

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aaron_do

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Re: How to choose Rp, L, C for cascode LNA?
Reply #19 - Feb 16^th, 2014, 6:03pm

Hi baab,

its been a while since I did those analyses, and I suspect they may be inaccurate for such a high gm/Cgs (Your value of Ls is too small to be practical). As I remember, the equations are based on a rather simplified transistor model.

For the impedance matching you are right, you don't need to add an additional matching network. But remember to take into account the gate resistance of the transistor, and Lg's series resistance. As RFICDUDE pointed out, you may want to lower the fT of your device which will lead to a more reasonable value of Ls.

regards,
Aaron

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baab

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Re: How to choose Rp, L, C for cascode LNA?
Reply #20 - Feb 17^th, 2014, 12:13am

Thank you. I read about the adding of the additional capacitor. However, it makes the implement more practical. In simulation, my my circuit above should be fine, right?

To be practical, please what is the range of Ls? I just simulated NFmin with Ls swept. As Ls increases, NFmin increases significantly.
With Ls = 10um, NFmin is about 1.99dB at Vgs = 0.6V.

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aaron_do

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Re: How to choose Rp, L, C for cascode LNA?
Reply #21 - Feb 17^th, 2014, 6:27pm

What do you mean by Ls = 10um? As far as I know, a practical value will depend on your implementation and layout.

If you are doing using a down-bond (bondwire) as Ls, then the down-bond inductance would be roughly 0.5 nH. You would also need to take into account the layout routing from the source of the transistor to the bonding pad. This could be 0.1nH for example, but its better to model this. So the total would be roughly 0.6 nH.

If you are using an on-chip Ls, you can make Ls smaller. But you need to take into account how accurately you think you can model Ls (including parasitic inductance).

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baab Senior Member Offline Posts: 178 EA	Re: How to choose Rp, L, C for cascode LNA? Reply #22 - Feb 17^th, 2014, 11:58pm Hi, Aaron. Quote: What do you mean by Ls = 10um? Sorry for the mistake. I will need to look it up again. I don't remember exactly the value right now. We have the lower limit for inductance because the parasitic inductance of bondwire, right?
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aaron_do

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Re: How to choose Rp, L, C for cascode LNA?
Reply #23 - Feb 18^th, 2014, 6:51pm

Quote:

We have the lower limit for inductance because the parasitic inductance of bondwire, right?

It depends on your design. If you reference all of your ground's to the transistor source, then the ground downbond won't have any effect. Its easier to do in a differential circuit due to the virtual ground. The short answer is "no", the bondwire inductance doesn't limit the amount of source degeneration. The lower limit is all of the parasitic inductance due to your routing.

Aaron

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