hi all,

i am designing an array of amplifiers (say 100) and need to bias all of them in the same way.

i can generate a 100 bias currents and mirror them in the amplifiers (also need to generate cascode bias voltages) or i can generate a generic bias voltage and connect it to the gates of all the current mirrors in the amplifier.

i am keen on just distributing bias voltages (including cascodes) with a high series resistor (~10k) between the various bias lines.

comments anyone ?

that is how i usually do it ... anyone in the "distributing voltages" camp ?

carlgrace wrote on Feb 11^th, 2014, 2:36pm:


A couple of observations - in addition to IR drops causing problems when matching voltages, process and temperature mismatches between components are issues if the distance between the devices is large. Beware, this can also bite you if you route current to create a voltage. I know of a group that tried to create local voltage references routing a current and ran into trouble because the local resistance didn't match the master one. Temperature, process, and packaging stress all conspire to make devices different across the die.

Avoid errors caused by the conversion device: if you are trying to create a voltage then you should generally route a voltage. (You might have to Kelvin connect things to avoid IR drop problems.) On the other hand if you want to create a current (for example, by biasing the gate of a local current source) you should route a current and mirror it locally.

When you have a huge array of devices it may make sense to do a little of both - make the layout tall and skinny so the biased devices are adjacent and have them all share the same local bias. You might be able to make this work for (guessing) 10 amplifiers without the end amplifiers debiasing. This means you will need ten of these sub-blocks to get 100 amplifiers, but you will only have to route ten bias lines. As Carl pointed out, you will have to be careful that the amplifiers don't crosstalk via the common bias line.

And for giggles I'm going to make Carl regret suggesting daisy chaining 100 biases since even a 5% error in the mirror gain will cause a 13,000% error in the last one. I will leave it as an exercise for the reader to calculate the random mismatch and thermal noise errors of the last device (hint, ~sqrt(200)x).  

Last point, which has already been touched on, but a voltage always comes with it's reference, so when you distribute a voltage, ideally you need to distribute its reference too. Although a capacitive load won't result in any DC drop along the line, there could be an AC drop. So any noise/transient could be a problem...

BTW, I'm not saying anything about the method you've chosen since it entirely depends on your design/layout.


Aaron

harpoon wrote on Feb 12^th, 2014, 12:29am:

This is done all the time with good success but as aaron said, voltages come in pairs so you are also routing to the source - which is actually where the problem comes from since it is resistance in the source line that causes debiasing or worse, if signal or noise currents flow through that line the IR drop in it will modulate the gate-source voltage. This is not a reason to avoid routing a common gate voltage - just make sure you check the effects of metal resistance in the source return line because it can be unexpectedly high. Making the overdrive of the current source as large as possible will help and is always a good idea.

Quote:

I've also done this - you will have a slow startup but that might not be important. Gate leakage could be important, yet it may not be modeled so check (I don't know if gate leakage would create noise problems with a large series resistance - base currents in BJTs do. Does anyone know?).

One thing I found totally counter-intuitive is that routing a small current is less noisy than routing a large current if you are filtering the resulting voltage generated (which could be either an IR or Vgs). The reason is that the AC impedance the current sees is 1/(sC) and the magnitude of the total thermal noise is less with a smaller current than with a larger current. Think about it - a current that is twice as large has sqrt(2) more noise. But I suppose if you made it too small you would run into 1/f noise and mismatch problems.

Of course, all this advice could be total overkill - it depends on your application.

And anyone familiar with Carl Grace's work knows he isn't a bonehead .

RobG wrote on Feb 12^th, 2014, 9:33am:


It was interesting to read and think about it. It is counter intuitive indeed! But it is only true if you use the same resistor to form the RC filter and convert the current to voltage. If you add an RC filter with a separate, high enough R to make the filtering pole approximately independent from the current-to-voltage converter resistor, then you get back the familiar higher signal power, higher signal-to-noise ratio.
The new, higher value resistor should not increase your noise, since it will be still kT/C. Of course it needs more area.

Here is my simple calculation:
If we use higher current to generate the same voltage, then the resistance would be proportionally lower.
v=i*R  &  vn^2=c*i*R^2      p=1/RC
v'=2i*R/2  &  vn'^2=c*2i*(R/2)^2=c*i*R^2 /2 = vn^2 /2 --> vn'=vn/sqrt(2)      p'=1/(R/2)/C=2/RC
So in the double current case we have 1/sqrt(2) voltage noise if there is no capacitance. But if there is a cap, then the bandwidth of the RC filter increases. This results in increased noise. But if the filtering pole is independent of the current-to-voltage generating resistor, then higher current means lower noise.

loose-electron wrote on Feb 17^th, 2014, 2:08pm:


i like this idea ... distribute current globallly ... and then again locally.