Hello Everyone,
In one of the paper on Frac-N PLL design, I observed that they used 4 seperate regulators, one for each of its sub-blocks: LC-VCO,Feedback divider, Post divider & (PFD+loop filter).

Qualitatively, I feel that we need only two regulators.
first regulator for (VCO+Post divider).
second regulator for (feedback div + PFD + loop filter).

Because, post divider output clock is synchronous with the VCO and there is no cross coupling between them. Hence i think we can keep them under the same regulator.

Similarly, feedback divider and PFD works on the fractional VCO divided clock and they can share the same regulator.

Can anyone please comment on if my understanding is correct ? how can we quantitatively evaluate this?

Thanks
Rajkumar

Also be sure to reference your loop filter capacitor to the same supply that the VCO control is referenced to.  That way power supply noise will be common mode (to first order).