I am designing frequency divider and reference buffer for a RF-PLL.
I have doubts regarding the way to simulate for jitter/phase noise contribution of these 'driven' circuit using cadence spectre.
After reading some posts on this forum ( http://www.designers-guide.org/Forum/YaBB.pl?num=1224609785 ) and reading the spectre RF manual, I have concluded that I should use the following pnoise settings while simulating a divider -
engine = shooting (in pss options)
noise type = jitter
sweeptype = absolute
Sidebands = full spectrum
Crossing direction = rising (as the PFD will sense only the rising edge)

Once the sim is complete, I do direct plot -> Main form -> pnoise jitter and plot Jee (rms in seconds)
To calculate rms jitter, I square the PSD (which is originally in seconds/sqrt(Hz)), integrate in my band of interest and take a square root.

I have a couple of doubts in this method.
1. Is it required to multiply this number by sqrt(2)? We do that while we compute jitter from phase noise plot to take care of both upper and lower band noise. I wonder if the Jee PSD which I get has all the noise power in single side band or here also I need to multiply the integrated number by sqrt(2).

2. My divider has CML stages, and then output clock is converted in CMOS level using a D2S. In this scenario, which method is recommended as engine in pss, harmonic or shooting. Do these methods affect accuracy of the result or do they just affect the simulation time?

3. For the reference buffer, which will get the clock as sine wave (and not square wave), do I need to change any of the above mentioned settings? Does it make more sense here to use harmonic balance instead of sources? The reference buffer will take differential sine wave clock as input and will give square wave single ended clock as output.