Hi, Folks!
Tell me, please, about advantage or disadvantage of using p/n mos transistor as bypass filter between, for example, VDD and GND.
C-V characteristics of mos  capasitor has two flat regions, which equal to Cox (at accumulation and strong inversion) at Low frequencies. Also, at High frequencies, capacitor, based on mos transistor, has extremely lower capacitance than Cox after threshold.
1. How to predict at which frequences this occur?
2.Cox may be obtained in "full closed" or "full open" region of transtor. I mean, it is equivalent that we use (for PMOS) G - on GND, (S,D,B - VDD)  or G - on VDD, (S, B, - GND, B - VDD) at Low frequencies. The different situation for NMOS...It is true?
3. Why, in many cases, Gate of active MOS transistor is connect to VDD via resistor (~1K). In contrast to connection to GND...  On my experience, all floating gate for active device we directly connect to GND without any things about ESD stress.  The same classic Trigger Schmidt may have direct gate connection to VDD.
4. How to calculate (fast, intuitive)  W/L ratio of transistor based on  cutoff frequency in case his connection from VDD to GND .
Please, give me some advise, any things, comments....
 Many Thanks!