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Self-checking testbenches for model validation (Read 91 times)
Dushyant Juneja
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Self-checking testbenches for model validation
Mar 24th, 2014, 2:39am
 
Hi,

There has been some talk about developing self checking test-benches for analog verification in a mixed signal design. I am still not clear how exactly the test-bench is given the intelligence to check and update itself with changing model needs. Is there some whitepaper/design example available to get the practical details?

Dushyant.
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Andrew Beckett
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Re: Self-checking testbenches for model validation
Reply #1 - Apr 7th, 2014, 2:40pm
 
The term "self-checking" is often used in the context of Assertion-Based Verification. This is where you put assertions in the design using (for example) PSL (Property Specification Language) to ensure that certain conditions are met - which then ensures that you can observe problems (bugs) in the design at the site of the problem rather than trying to necessarily observe them from the outside.

Maybe that's what you've seen?

Regards,

Andrew.
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Ken Kundert
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Re: Self-checking testbenches for model validation
Reply #2 - Apr 8th, 2014, 12:12am
 
You might try taking a look at Designer's Guide Documents or Designer's Guide Classes.

-Ken
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Dushyant Juneja
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Re: Self-checking testbenches for model validation
Reply #3 - May 13th, 2014, 2:32am
 
Thanks Ken, Andrew for your replies. I'm sorry for the delayed response on my end.

I guess I went a bit too ambitious with the term "self-checking". I thought it gets some facility to update itself with the design, hence have some facility to "check itself". I understand now that it's just an automation of manual looks into the design. Of course, at a much deeper level.

Nevertheless, even building an exhaustive testbench, straight from the specs, is pretty challenging. Is there some literature available in this regard?

Thanks for the replies!

Dushyant.
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