Lucho
New Member
Offline
Posts: 5
Bucaramanga - Colombia
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Hi have the following verilog-a block for a random number generator:
--
// VerilogA for Example, RdnGen, veriloga
`include "constants.vams" `include "disciplines.vams"
module RdnGen(out);
output out; electrical out;
integer randn; integer sign;
analog begin
randn = $random %60; sign = (randn < 0) ? 1:-1;
@(initial_step)
$strobe
("Rand\t\t",randn, "\n", "Sign\t\t", sign, "\n\n\n\n\n");
end endmodule ~
--
I don't understand why every single time I run this code the "randomly" generated number is always the same.
Any hints ?
Thank you,
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