bigball
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US
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Hi:
Does VerilogA have the same syntax as verilog_AMS?
I'd like to add a capacitor and resistor to my verilogA modeling, is the following code correct? By the way, how do I add thermal noise to the resistor? Thanks.
inout a,b; electrical a,b; parameter real r=4K from (0:inf); parameter real c1=200p from (0:inf); parameter real c2=6p from (0:inf); electrical int;
capacitor #(.c(c1)) C1(a, int); capacitor #(.c(c2)) C2(a, b); resistor #(.r(r)) R(int, b)
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