Hi,

I have a question about the gate-oxide breakdown of RF CMOS switch. Usually the gate and substrate are bootstraped with large resistances (in the order of tens of kilo ohms), and the drain/source usually bias at higher voltage instead of at 0V. For example, in a process with nominal breakdown voltage equals to 2.5V, the drain/source is biased at 2.5V, and the gate swithing voltage is 5/0V. When the gate is biased at 5V, the gate-bulk voltage is 5V, which exceeds the gate-oxide voltage of 2.5V. I don't undertand why this is not a problem here, seems to be related to the bootstrap at both gate and bulk. Can anyone explain this?

Kind regards,


Junior RF man

Hi,


I asked a similar question a while ago. The answer given was because when the transistor is ON, the channel is at 2.5 V, not 0 V. So there is no breakdown issue...seems correct to me.


regards,
Aaron