rf_man
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Hi,
I have a question about the gate-oxide breakdown of RF CMOS switch. Usually the gate and substrate are bootstraped with large resistances (in the order of tens of kilo ohms), and the drain/source usually bias at higher voltage instead of at 0V. For example, in a process with nominal breakdown voltage equals to 2.5V, the drain/source is biased at 2.5V, and the gate swithing voltage is 5/0V. When the gate is biased at 5V, the gate-bulk voltage is 5V, which exceeds the gate-oxide voltage of 2.5V. I don't undertand why this is not a problem here, seems to be related to the bootstrap at both gate and bulk. Can anyone explain this?
Kind regards,
Junior RF man
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