Hi, everyone,
I have simulated a TITO VCO in Cadence by PSS and Pnoise (Ref. 08_JSSC_CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits). But, I found that the Phase noise is variable and it seemed that the value of phase noise can be smaller with small "estimated line width"

Is there anybody knows whether there exits a relationship between the phase noise and the estimated line width?