I am looking here On Figure 8, Page 4. :
http://cmosedu.com/jbaker/papers/2011/Systematic_Design_of_Three_Stage_Opamps_us...

What I see is that the output buffer does not have any defined current. For example, when I run the DC simulation and when both inputs to the output buffer are around Vcm=0.9V, I have really huge ~300uA current in each node.

I was curious what would be a way to reduce that big current and at the same time keep the architecture really small?

I tried to bias the bottom node of NMOS transistors from a NMOS Vbiasn4 source, but that did not quite work.

Another thing I noticed is the fact that with this architecture of the Output Buffer and 1.8V process, when I have my input stage of Op-Amp (in my case it is folded cascode one), each output swings only from 100mV to 1.7V, i.e. total swing is 1.6V, but it is supposed to be from 0V to 1.8V. Any ideas what other parameters of the circuit I can play with to get a wider swing?

And of course, it is quite strange that the bottom NMOS gate connections are just floating. Where that supposed to go? If I bias them, then of course I force known current in all legs of output buffer, but it doesnt work, if I Gate-Drain connect the inner NMOS bottom transistors the circuit works, but I have crazy currents.

And another thing I noticed is the fact that with this scheme I have kinda low (1.9k) Overall gain. Which is not what it supposed to be.

Also, the diode connected NMOS in the middle of inner legs I assume is the device which "supposed" to help the output swing. But, playing around with its values does not bring that result, at most I can swing outputs from 100mv to 1.7V only.

Let me know if someone has some thoughts or additional ideas about that circuit.

To get an accurate DC bias point try putting a big (100 MEG) resistor from the - output to the + input, another big resistor from the + output to the - input, and then two big capacitors (1 uF) from the inputs to ground as seen in Fig. 26.38 of Baker's book. Then do an operating point simulation (that is, a .op sim). Using this setup you can also do a DC sweep and vary VDD to check to see how well the biasing works. If the design has a start-up issue (page 887) then use a DC sweep where you hold one input at 900 mV (VCM = VDD/2) and sweep the other input as seen in, for example, Fig. 26.33.

You can't look at the biasing of an op-amp by applying DC voltages to the inputs (you've got to have feedback for a stable DC operating point). Using DC voltages on the op-amp's input, with a class AB output, may result in large currents in the class AB stage as you've already indicated since some devices will triode and the gain will drop.

I also responded to your June 8 post...it appears you are copying designs without understanding how they work, or how to setup appropriate simulations, and then getting frustrated.