Hi experts,

I have the following requirements for my frequency synthesizer PLL

center frequency= 700MHz, channel bandwidth=300KHz
channel switch time<=100us
Phase noise<= -100dBc/Hz@ 1MHz offset

I want to make the PLL as low power as possible (<700uW). Which is the most suitable architecture:
All digital PLL
Integer N PLL (Type 1 or Type2)
Fractional N PLL

With type2 integer N PLL: Loop BW=1/10th of channel BW=30KHz. This makes it difficult to achieve channel switch time of <100us

Your phase noise is the big issue. All digital at that phase noise number? I doubt it.