Hi everyone,

I have a question when I simulated a simple adder by cadence virtuoso. I've designed a 64-bit adder and would like to make a simulation. But it seems too boring when I do so because there are almost 200 pins. That is to say if I just use vpulse (NCSU_Analog_Parts -> Voltage_Sources -> vpulse) in this process, I need more than 100 voltage sources in my design that will be boring and time consuming. Are there some other kind of sources that can be used in this situation or some other method?

Thanks a lot!

Thanks for your response, Ken.

I know the Verilog-AMS and it should be a good choice, but I just wonder if I can do this simulation by cadence spectre. Maybe I can extract the netlist of the model from the schematic and simulate it by coding manually. It seems a boring work too.

-Wayne