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AMSA

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Problem with non-overlap circuit
Aug 06^th, 2014, 5:35am

Hi guys,

I've tried several non overlap circuits, just google in the images section for non overlapping circuits that you'll those who I am reffering to.

Here I present the non overlap circuit done with 2 NAND and 1 NOT gates then 2 delay lines in each branch.

Picture:

The problem here is that I can't proximate both the rise and fall edges even more. The only way is to remove the delay lines. Even though if I wish to separate them a bit, using the delay lines it's impossible.

I am using 500Mhz of switching frequency (VPULSE).

Basically the question here is how can I proximate the edges?

As I said, I did the same with other types of non overlapping circuits but the result was pretty much the same.

If I add more delay (2) the edges get more far away from each other. If I add only one more delay (3) the wave gets a strange shape. It only works with pairs. Why this happens?

If I reduce the size of the transistors in the delay line the signal gets strange because it can't supply current to the NAND because of its size.

My tech is UMC130.

Kind regards.

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boe Community Fellow Offline Posts: 615	Re: Problem with non-overlap circuit Reply #1 - Aug 11^th, 2014, 12:09am AMSA, if you use an inverting "delay line", you change the logic function - so the circuit can no longer work. If you think about the circuit you will see that the length of the delay line defines the duration of the both-off state. - B O E
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AMSA Community Member Offline Posts: 46	Re: Problem with non-overlap circuit Reply #2 - Aug 13^th, 2014, 8:16am I see. But how do you suggest the delay line implementation? Isn't using NOTs? NOTs aren't made of inverters? I have seen this circuit around the web. But in one or two books too. Regards
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carlgrace Senior Member Offline Posts: 231 Berkeley, CA	Re: Problem with non-overlap circuit Reply #3 - Aug 13^th, 2014, 2:03pm What do you mean "proximate" the rise and fall edges? The minimum you can reliably have for non-overlap depends on your process. So does the minimum rise/fall times.
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boe

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Re: Problem with non-overlap circuit
Reply #4 - Aug 14^th, 2014, 3:50am

AMSA wrote on Aug 13^th, 2014, 8:16am:

I see. But how do you suggest the delay line implementation? Isn't using NOTs? NOTs aren't made of inverters? I have seen this circuit around the web. But in one or two books too.

Regards

AMSA,
but overall, the delay line needs to be non-inverting (i.e. have an even number of inverters).
- B O E

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AMSA

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Re: Problem with non-overlap circuit
Reply #5 - Aug 14^th, 2014, 5:56am

BOE, but that wasn't what I've made? If you notice on the circuit, the feedback is taken after 2 delays, that is, two inverter - so to say after an even number of inverters.

Isn't correct?

Well, the idea that I have after reading about his subject was that one can control the non overlap space by inserting a number of (EVEN) inverters on the feedback. That's correct. However, after I've done my readings, I put that into practice and I found that I canno't create an accurate delay (space between the signals) between the signals in a way that I can do it in a fine manner, that is, have something like a fine tune of the delay.

I've enven tried with only two inverters (even) with small values of W/L, somsthing aroung 200n/160n and even though I didn't managed to get that fine tune of the delay.

That's why I asked this here.

Regards.

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wendyyang100 New Member Offline Posts: 7	Re: Problem with non-overlap circuit Reply #6 - Aug 14^th, 2014, 7:43pm Hi, I think the "fine tune delay" is not easy to get, since the delay of inverter strongly depends on the process. And the delay caused by layout may count sometimes. wendy
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boe

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Re: Problem with non-overlap circuit
Reply #7 - Aug 15^th, 2014, 5:06am

AMSA,
AMSA wrote on Aug 14^th, 2014, 5:56am:

BOE, but that wasn't what I've made? If you notice on the circuit, the feedback is taken after 2 delays, that is, two inverter - so to say after an even number of inverters.

Isn't correct?

Yes, it is. I was referring to your earlier post:
AMSA wrote on Aug 6^th, 2014, 5:35am:

... If I add only one more delay (3) the wave gets a strange shape. It only works with pairs. Why this happens?

AMSA wrote on Aug 14^th, 2014, 5:56am:

... However, after I've done my readings, I put that into practice and I found that I canno't create an accurate delay (space between the signals) between the signals in a way that I can do it in a fine manner, that is, have something like a fine tune of the delay.

I've enven tried with only two inverters (even) with small values of W/L, somsthing aroung 200n/160n and even though I didn't managed to get that fine tune of the delay. ...

You can influence the value of the delay chain by sizing and loading.
However, as already mentioned by carlgrace, there are fundamental limits what you can achieve in your process (and under your operating conditions), also in terms of accuracy (variance).
- B O E

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« Last Edit: Aug 15^th, 2014, 6:52am by boe »

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AMSA

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Re: Problem with non-overlap circuit
Reply #8 - Aug 15^th, 2014, 12:18pm

Ok BOE I understood why you said that. My mistake. Can you elaborate the charge and loading?

So maybe I'm at the process limit, is that it?

Perhaps I should have given the set of operating conditions and the process I am using:

The non overlap circuit is operating @500Mhz;
The process is 130nm from UMC;
The transistors I am using are the 3.3V transistors;

Regards.

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boe

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Re: Problem with non-overlap circuit
Reply #9 - Aug 18^th, 2014, 6:44am

AMSA,
in my tech, a straight-forward non-overlap circuit with 3.3V transistors (3.3V, 27 degC, typ. process) and 2 inverters can achieve a gap of about 200 ps. I am not sure it makes even sense to go below that to ensure proper operation over PVT corners.
If you want to increase the gap, you can increase the load of (i.e. add cap to) internal nodes...
- B O E

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