carlgrace
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Not that it is germane to your design but I thought I would comment a bit about deep n-well. At least in TSMC, the deep n-well is indeed a buried layer. Then, n-well contacts sink down to this layer to bias it.
As Wendy said, there is no "p-well" (at least in tsmc). Processes that have a p-well implant are often called "Triple well" because then you can isolate both n and p devices.
In a deep n-well process, your nmos devices are indeed implemented in the p-substrate, but, as Aaron said, this portion of p-sub is isolated by back-to-back diodes from the rest of the substrate, hopefully reducing noise pickup.
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