Hello,

I was reading Ken Kundert's paper "Predicting the Phase Noise of PLL-Based Synthesizers." Its audience I believe is primarily for ASIC designer's of PLLs, of which I am not, but am interested in learning the fundamentals. On page 16 it states, ".....while the noise from the PFD will all be in the edges and so will be independent of how long the CP is on." What I'm interested in is what's the phase noise contribution of a phase detector. I understand the statement above -- it makes sense that the more edges, the more noise (same concept as with the created clock itself -- if you divide it down you'll have less phase noise). However, I was looking at a Hittite PLL (HMC703LP4e). On page 15 of the datasheet (EQ 1), it shows an equation for the overall phase noise, as a function of various contributors. One of those contributors is the frequency of the phase detector, which is a denominator of the last term. Therefore, the higher the phase detector frequency, the lower the phase noise overall. Can someone help me understand the discrepancy? Thanks for any feedback.

For a given o/p frequency, increasing fref means decreasing N hence in band multiplication decreases.
1. charge pump noise spectral density depends on up/dn pulse width*Fref, hence cp noise will go up unless you redesign the PFD (very difficult, overlap time decided by the dead-zone).

2. Increasing reference frequency will also impacts in-band noise unless you use different crystal or some clean-up PLL.

Thanks,
Raj.