Designer’s Guide Community

circuit_cook Junior Member Offline Posts: 25	DAC at 110M Hz Dec 04^th, 2014, 8:12am Hi, all: For a DAC with 110M clock frequency in most recent digital CMOS process, is current steering the only suitable architecutre. I wonder if there are passive DAC options for this, I have problem with the current steering DAC because the current source noise is high. Judy
Back to top	IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: DAC at 110M Hz Reply #1 - Dec 4^th, 2014, 10:59pm At that rate, current steering is probably the best choice for most CMOS technologies out there. The CMOS noise has been studied a bit in these research IEEE JSSC papers on the subject.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

circuit_cook

Junior Member

Offline

Posts: 25

Re: DAC at 110M Hz
Reply #2 - Dec 5^th, 2014, 7:46am

Thanks for the above reply, that confirms my conclusion.
Now is there a simple solution to this? because our headroom is small, only 1.8V for cascode current source, current source noise is bad. To get a low noise at 400kHz, we have a large RC filter on the bias, but that (because of the large R) deterioate 10k noise even worse.
I read in the papers, some are talking about swiching the biasing circuit to reduce the flicker noise, the reduction can't be seen in simulation but can be seen in the lab. Does anyone get good results from that?

Judy

Back to top

IP Logged

RobG

Community Fellow

Offline

Posts: 569
Bozeman, MT

Re: DAC at 110M Hz
Reply #3 - Dec 5^th, 2014, 8:46am

It depends on your load, resolution, and what your process is. You say most recent process, but you are using 1.8V. That doesn't add up.

I agree with loose-electron in that switched current is going to be the fastest, but depending on your specs other topologies can work at 110MHz.

Capacitive DACs are plenty fast. ([3] Wang, F.-J.; Temes, G.C.; Law, S., "A quasi-passive CMOS pipeline D/A converter," Solid-State Circuits, IEEE Journal of , vol.24, no.6, pp.1752-1755, Dec 1989).

If you can drive your load with an RC filter you can probably do the design with a tapped-R dac.

I can't say if these are appropriate for your design since you haven't given enough information.

Back to top

IP Logged

circuit_cook

Junior Member

Offline

Posts: 25

Re: DAC at 110M Hz
Reply #4 - Dec 5^th, 2014, 12:14pm

Hi,

The load is not large, only 2p, which is a control port. The resolution is 10Bit. the process 28nm, but the DAC uses IO device, so it is 1.8V, and it needs 1V output swing.
Right now the current DAC does have a RC filter connected at the output, the clock is 110MHz, but the reconstruction filter is 1.6MHz bandwith.
I thought about tapped R, but the concern is speed and glitch.
Need to read the pipeline converter paper. Also I am taking a poll here if anyone has success with a passive DAC at 10Bit 110MHz, the signal bandwidth doesn't need to be 50MHz. only couple of MHz.

Thank you.

Back to top

IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: DAC at 110M Hz Reply #5 - Dec 8^th, 2014, 6:32pm if the signal BW is as low as you described, why the high clock rate? Also, the flicker noise of current sources in a HF switched current system needs to be studied a bit more because how you do the switching, rotating the current sources, etc effects the noise product put out.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

circuit_cook Junior Member Offline Posts: 25	Re: DAC at 110M Hz Reply #6 - Dec 9^th, 2014, 7:53am Hi, The DAC is in a Digital PLL, and the clock rate is 110M, so that is the reason for the high speed.
Back to top	IP Logged