Y,
More info would be good. If it is the N+ buried layer underneath the
npn transistor, then it serves several functions:
1) Lower collector resistance of the npn, lower collector resistance
means lower saturation voltage.
2) It suppresses the beta of the parasitic vertical pnp formed by
the p-base, E, n-collector, B, and p-wafer, C. The idea is that
if the base is more highly doped than the emitter, then Beta
will be low suppressing latch-up and minimizing current
injection into the substrate during saturation.
3) N buried layer also prevents the base depletion region from
reaching the substrate, punchthrough, at high Vcb.
Now if you meant the buried layer under a vertical PNP, that is,
a different thing
Sheldon