josef_sous
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hi all, i'm new in verilog A so I've got some basic question. well i'm trying to simulate the influence of the TDC quantization noise in ADPLL close loop . fot that i want to add some quantization noise in the form of a uniform distribution so i write this code: // VerilogA for adpll model, VNoiseuniform, verilog a
`include "constants.vams" `include "disciplines.vams"
module VNoise_uniform(out); output out; electrical out; parameter real half_LSB =-10e-12; //
real noise,end_range; integer seed;
analog begin @ (initial_step) begin seed = 0; // Initialize the seed just once end_range =10e-12; // A variable end noise = $rdist_uniform(seed,half_LSB,end_range);
V(out) <+ noise;
end endmodule /// well while i'm running it on spectre tran simulation i got something that's look like a uniform noise but when i examine the noise via noise simulation(in db) i get the lower bound that i can get ,for example i suppose to get a -224db for the value in the code and the simulation plot's is -6.5Kdb!!! well what i'm doing wrong? thanks !
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