Hello everybody, with this code I want to realize a substractor and amplifier and a multiplier. The problem with this code is that each time simulate it with smash, I have the following errors

ERROR: In architecture 'SIMPLE' of entity 'AMPTIMESSUBVREF'
E:/Me/vhdl-ams/test VSR/ampTimesSubVref.vhd(10): imple of ampTimesSubVref is
Characteristic number (5) does not match simple simultaneous statements (4)
Characteristic number = scalar free quantities (1)
                     + scalar through quantities (4)
                     + scalar interface quantities of mode out (0)
                     - scalar quantities associated with formal quantities of mode out (0)
ERROR: cannot generate model code for 'SIMPLE'
ERROR: cannot specialize model 'SIMPLE' for instance 'AMPTIMESSUBVREF'
ERROR: elaboration of 'WORK.AMPTIMESSUBVREF(SIMPLE)' at top level failed

library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;

entity ampTimesSubVref is
 port (
   terminal in1, in2, out1 : electrical );
end entity ampTimesSubVref;

architecture simple of ampTimesSubVref is
 terminal t1, t2 : electrical;
 quantity vin1 across input1 through in1;
 quantity vout1 across iout through in1 to t1;

 quantity vref : real := 400.0;
 quantity vin2 across input2 through in2;
 quantity vout2 across iout2 through in2 to t2;

 quantity vin3 across input3 through t1 to t2;
 quantity vout3 across iout3 through out1;
 
begin
 vin1 == 220.0 * sin (2.0 * 3.14  * 50.0 * now);
 vout1 == ((vin1*vin1)/(230.0*sqrt(2.0))); --amplifier
 
 vin2 == 220.0 * sin (2.0 * 3.14  * 50.0 * now);
 vout2 == vref - vin2; --substractor

 vout3 == vout1*vout2; --multiplier
 
end architecture simple;

Thanks for your comprehension.