I'm fairly new to Verilog-AMS and trying to model a gated ring-oscillator. I'd like to be able to freeze, reset and then re-enable the oscillator with the reset phase using input signals. I generate the phase using
Code:phase = 2*`M_PI*idtmod(freq*fv,0.0,1.0,-0.5);
and my oscillator output is
Code:V(OUT) <+ offset + ampl*sin(phase);
where frequency is my output frequency and fv is a variable I set depending on the crossing of enable. Once the enable signal goes low, fv becomes 0 and the state of the ring-oscillator is frozen. When enable goes high, the phase continues to integrate.
I have tried to apply a reset of the phase by detecting the crossing of my reset signal but since idtmod is outside of this, the phase of the oscillator always returns to the phase it was at before I froze its state - rather than continue from the reset state.
I'd much appreciate advice on the following - Whether it is possible to reset the phase of idtmod? And if not, is there another way to model a ring-oscillator with this function using verilog-ams?