Good morning everybody,

I am a new user and I knew about the forum from the book the designer's guide to Verilog-Ams.

In our project we just decided to move toward a system level Verification using Real Number Modelling for the Analog Blocks.
I had some problems in modelling the Charge Sensitive Preamplifier. Basically I modelled it in RNM considering the transfer function of the CSA. The behavioral model works fine but I have a problem with the input port.

My input port is a wreal and is fed by a current pulse (electrical signal). The problem comes when the conversion between electrical to wreal signal is made. I'm not able to model the input current in such a way I could get a proper value of the voltage at the output.
I checked about defining a new discipline but I didn't get how to fix it.

Any suggestions?

Thanks and Regards

Dimitri