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Decimation Filter in Verilog - can I use Blocking assignment (Read 2161 times)
jdp
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Decimation Filter in Verilog - can I use Blocking assignment
Mar 31st, 2015, 8:19am
 
Hi,

I am trying to realize a CIC decimation filter (for delta-sigma ADC) in Verilog.

I want to know whether to use NON-BLOCKING ASSIGNMENT <= or BLOCKING ASSIGNMENT = in Verilog implementation of the constituent integrators and differentiators.

E.g., for the integrator section (image attached), commonly cited code is like:

always @ (posedge clk_in)
begin /*perform accumulation process*/
acc1 <= acc1 + ip_data;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end


I want to know if I can use Blocking assignment = instead of <= above - shouldn't that be better?
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acc.PNG

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jdp
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Re: Decimation Filter in Verilog - can I use Blocking assignment
Reply #1 - Apr 5th, 2015, 1:41am
 
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