vahid
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hii i write this verilog-a for variable capacitor and i test circuit in hspice but capacitor don't change While i expected capacitance change sinusoidal please help me
`include "constants.vams" `include "disciplines.vams" module vccap(Cp, Cn, Vp, Vn); input Vp, Vn; inout Cp, Cn; electrical Cp, Cn, Vp, Vn; real C; parameter real C0 = 0; parameter real CS = 2.5p; analog begin C = V(Vp,Vn); I(Cp,Cn) <+ C * ddt(V(Cp,Cn)); end endmodule
hspice test :
.hdl vccap.va .options post=1
x1 1 2 3 4 vccap
vi 3 4 sin( 0 1 500k)
.tran 2n 500us
.PROBE tran cap(1,2) cap(1) cap(2) .end
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