Hi adie_N,

I think you have to measure it in open-loop configure, even because, the comparator is to be used in a open-loop configuration.

I don't know if that input offset is high or not, because I don't know where he will be used and what is the performance and specifications of it.

But in first place, assuming that you are doing correctly the offset measurement, that is, that you have a correct setup for the offset measurement, try to use a very small step in the DC analysis. For example, 1uV or 10uV. Don't forget to tighten the span of the dc sweep so that the simulation don't take too long.

Give the feedback after you try.

Can you try a smaller step size? Imagine, 0.1uV just to compare.

Well, if it is the same value then the input offset is 1.6uV. This might have to do with accuracy vs resolution, but I don't know how to explain this. Maybe someone else can. I think it is a good value, but it will depend on the application.

Have you compared to similar works? To similar works that shows the input offset value.

loose, he is simulating in a virtual world and in schematic.

AMSA wrote on May 29^th, 2015, 5:59am:


Yes but he is talking about putting it onto 130nm CMOS somewhere along the way, and systematic offset won't matter if the matching error offset is much larger.