Hello everyone,

i am trying to simulate the accuracy of a delta sigma modulator (first order). It is a fully-differential switched capacitor integrator with a latched comparator. Transient simulation works, the question is how to evaluate the bitstream to get the accuracy for a given DC input voltage. Is it possible to perform a PSS, PAC or Pnoise simulation of the modulator?

Thank you in advance.

Thank you.
What have you used for counting matlab or a model directly in cadence.
Any idea concerning PSS, PAC or Pnoise simulation.

I have some experience with PSS, PAC and PSTB applied to fully-differential OTA's with SC-CMFB. I have also tried it now for the DS modulator but it did not converge.
For Simulation i have now written a Verilog-A model for counting the one's the bitstream for 2^N samples. Works fine, but is not satisfying in therms of simulation time and disk space.

My partner uses PSS for continuous time DSMs. He models the comparator with an ideal unity gain buffer so there isn't any switching. I don't know if it would work with switched capacitor designs unless you did a continuous time equivalent. Additionally, I don't know how accurate his results are but they seem to be ballpark.