I used dummy devices. All terminals of NMOSes connected to ground and PMOSes terminals connected to VDD.
However, if the foundry delivered such a solution it should make a trick. It all depends how devices are manufactured (what are the technology steps one after another). In case of two matched transistors, additional poly strips should ensure that environments for the outer boundaries of gate_1 and gate_2 are the same as for the inner boundaries of these gates (environment between gate_1 and gate_2):
dummy --- gate_1 --- gate_2 --- dummy
Without dummies polys you would have
??? ----- gate_1 --- gate_2 ------- ???
thus an etching can be different between gates comparing to the outer parts of the gates.
If you have a possibility, ask this question to your foundry Field Application Engineer (FAE) and let us know.