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cheap_salary Senior Member Offline Posts: 162	Which case can generate lower phase noise in band ? Aug 19^th, 2015, 5:58am (1) fcmp=25MHz, fvco=800MHz, Ndiv=32, LoopBW=100kHz fout=fvco/8=100MHz (2) fcmp=25MHz, fvco=3200MHz, Ndiv=128, LoopBW=100kHz fout=fvco/32=100MHz I want to get 100MHz signal for both cases. I assume integer-N PLL synthesizer. Which case can generate lower in-band phase noise regarding fout=100MHz ?
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Which case can generate lower phase noise in band ? Reply #1 - Aug 21^st, 2015, 10:57pm As the division of the feedback divider gets larger your phase noise gets worse. Keep the divide ration on feedback a low number where possible. No rigorous math proof provided, I am sure someone else might have something.
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cheap_salary

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Re: Which case can generate lower phase noise in band ?
Reply #2 - Aug 21^st, 2015, 11:24pm

loose-electron wrote on Aug 21^st, 2015, 10:57pm:

As the division of the feedback divider gets larger your phase noise gets worse.

Its effect is relative small.

My opinion is that both 800MHz and 3200MHz PLL give almost same in-band phase noise regarding fout=100MHz if PLL synthesizer is Integer-N.

However I expect 3200MHz PLL show better in-band phase noise if PLL synthesizer is Fractional-N.

And 3200MHz PLL has advantage about occupied area for loop filter, if charge pump current value is same.

================================================== ==
Lpll=Ndiv^2 * Lref
Lout=Lpll / Nout^2=(Ndiv/Nout)^2 * Lref

Lpll : in-band phase noise of PLL
Lref : in-band phase noise of reference clock, feedback divider and PFD.
Lout : in-band phase noise of fout=100MHz

(1) Ndiv=32, Nout=8, Ndiv/Nout=4
(2) Ndiv=128, Nout=32, Ndiv/Nout=4

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loose-electron

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Re: Which case can generate lower phase noise in band ?
Reply #3 - Aug 27^th, 2015, 11:51pm

as a math exercise the effect may be small the reality in silicon is something else.

large divide numbers in the feedback path lead to more phase noise

If you have ever done a PLL for video timing recovery you end up with a PLL that has a divide ratio equal to the pixels per line of the video image. (1024 for an example) that high divide ratio leads to a lot of phase variance while waiting for the next phase update to the charge pump

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cheap_salary

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Re: Which case can generate lower phase noise in band ?
Reply #4 - Aug 28^th, 2015, 7:24am

loose-electron wrote on Aug 27^th, 2015, 11:51pm:

If you have ever done a PLL for video timing recovery you end up with a PLL that has a divide ratio equal to the pixels per line of the video image. (1024 for an example) that high divide ratio leads to a lot of phase variance while waiting for the next phase update to the charge pump

I don't think so.
Such jitter is a total result of both in-band and out-band phase noise.

Comparison frequencies are same 25MHz between 3200MHz PLL and 800MHz PLL in my case.
So update periods are same.
And output frequency 3200MHz is divided to 100MHz.
Both 800MHz and 3200MHz PLL give almost same in-band phase noise regarding fout=100MHz if PLL synthesizer is Integer-N.

However I expect 3200MHz PLL show better in-band phase noise if PLL synthesizer is Fractional-N.

Some product tranceiver ICs, e.g. TI-CC1120 and SiliconLabs-Si4461, can give very excellent low in-band phase noise for 100MHz ~ 900MHz from 4000MHz-PLL.
This is a originate of my question.

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loose-electron

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Re: Which case can generate lower phase noise in band ?
Reply #5 - Aug 30^th, 2015, 12:40pm

You are talking divide ratios of 32, 8, and I am talking divide ratios of over 1000.

cheap_salary wrote on Aug 28^th, 2015, 7:24am:

loose-electron wrote on Aug 27^th, 2015, 11:51pm:

If you have ever done a PLL for video timing recovery you end up with a PLL that has a divide ratio equal to the pixels per line of the video image. (1024 for an example) that high divide ratio leads to a lot of phase variance while waiting for the next phase update to the charge pump

I don't think so.
Such jitter is a total result of both in-band and out-band phase noise.

Comparison frequencies are same 25MHz between 3200MHz PLL and 800MHz PLL in my case.
So update periods are same.
And output frequency 3200MHz is divided to 100MHz.
Both 800MHz and 3200MHz PLL give almost same in-band phase noise regarding fout=100MHz if PLL synthesizer is Integer-N.

However I expect 3200MHz PLL show better in-band phase noise if PLL synthesizer is Fractional-N.

Some product tranceiver ICs, e.g. TI-CC1120 and SiliconLabs-Si4461, can give very excellent low in-band phase noise for 100MHz ~ 900MHz from 4000MHz-PLL.
This is a originate of my question.

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Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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cheap_salary

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Re: Which case can generate lower phase noise in band ?
Reply #6 - Sep 6^th, 2015, 3:04am

(1) fref=32kHz, fvco=32MHz, fout=32MHz, Ndiv=1000, Nout=1
(2) fref=32kHz, fvco=320MHz, fout=32MHz, Ndiv=10000, Nout=10

Both (1) and (2) give almost same in-band phase noise regarding fout=32MHz,
since in-band phase noise contribution from feedback divider is far small than one from reference clock, PFD and CP.

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PSD_of_PLL_Output_Signal.png

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loose-electron

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Re: Which case can generate lower phase noise in band ?
Reply #7 - Sep 8^th, 2015, 12:27am

You keep coming back to the math model. The problem with the purely mathematical control system model is it does not account for the noise in the system, leakage of non ideal devices, bias currents, etc, and how it changes the voltage controlling the VCO.

The basic control system math does not account for that, and therein lies the problem.

For a mental picture of what is going on - take the PLL and the assumption that the loop is in lock, and the feedback path is opened up. (somewhat similar to a large divide ratio in the feedback path but the divide ratio is now approaching infinity)

In an ideal model the output of the VCO stays in phase with the input. In reality, the phase relationship drifts apart.

As the divide ratio gets larger, you are seeing more and more of that non-ideal drifting apart. The simple control model does not account for that.

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