Naga Kishan
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Posts: 4
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Hi,
I am using the following specifications to calculate the CMOS ring oscillator (Inverter-5stage)
PSS Engine: Shooting Fundamental frequency 3.1GHz Number of Harmonics 64 errpreset: moderate tstab: 333ns Oscillator . clk, gnd!
pnoise sweeptype. relative relative harmonic: 1 output frequency sweep range: 100K - 100MHz sweep type: log points per decade: 200 Maximum sidebands - 64 output - voltage - clk, gnd! Noise type - sources Noise separation - yes
I get the below attached phase noise value.
So, my main questions are:
1. Does this plot look reasonable?
2. what should be the phase noise value for a best ring oscillator (or in a range of dBc/Hz)
3. It is used for a divider circuit which CML logic which uses differential clocks ( clk and clkb ), so i designed with a inverter at the output of the oscillator. So, my question is does the phase noise differ for clk and clkbar (complement). does i need to use clkb for reference node in both pss as well as pnoise.
Thanks for your quick reply in advance.
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