I would like to generate fully differential quadrature signals of 950MHz using PLL Frequency Synthesizer from 1900MHz differential VCO with low power.

Currently, I realize this by D-FF based on master-slave latch structure using CML.
However current consumptions are fairly large.

Alternate idea I have is using two D-FFs based on TSPC where one is rising edge triggered and the other is falling edge triggered. And I use two inveter and two buffer after them for generating fully differential quadrature signals, i, ib, q and qb.
However this scheme is pseudo differential.

Quadrature VCO can not be candidate.

I use 0.15um-CMOS of vdd=1.5V.

If you know good technique, could you share it with me ?

agreed - poly phase or another reactive filter network structure