eeBismarck
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Posts: 6
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Hi Guys,
I am a beginner who is learning the verilogA by myself. Today I use the following code to model a capacitor
`include "constants.vams" `include "disciplines.vams"
module sjw_cap(p, n); parameter real C = 0; // capacitance inout p,n; electrical p,n; analog I(p,n) <+ ddt(C*V(p,n)); endmodule
when I run the transient simulation, and give the since wave as input. I find that the AC current is 0. Could you give me some clue ?
BR
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