1. Please post schematic, if I am not mistaken, in your case Mixer is driving a current mirror means charge pump current depends on error hence loop gain and hence stability depends on phase error. So you have to evaluate Stability very carefully. Better check current corresponding to zero phase and max phase error and do the loop dynamics calculation.

2. Very interesting Question, I haven't simulated unstable loop. Answer depends on what level of instability.
  A. If phase margin is poor(say 45deg), then peaking in the spectrum near the loop bandwidth, which makes integrated phase error worse.
  B. If phase margin is very poor, means control voltage oscillates. Based on the amplitude of the control voltage and vco characteristic's, o/p spectrum will have huge sidebands around the carrier frequency corresponding to control voltage avg voltage. IN the worst case control voltage oscillates between 0 to Vdd, hence carrier frequency corresponding to vdd/2 with spurs at an offset of loop natural frequency.

Thanks,
Raj.

If the loop is unstable it will not settle on frequency.
(will be seen as frequency oscillation around the reference frequency)

If the loop is marginally stable the control voltage will ring/overshoot if the frequency reference is shifted.

Go look through a textbook on PLL design there is a lot out there on control loops, zeta, damping and all that.