I'm working on a circuit that has two subthreshold diode connected transistors. I believe these two devices have the most impact on the variation in the circuit (with a Monte Carlo Analysis). I think it would be due to the exponential dependence on threshold voltage in the subthreshold region. I've managed to reduce the effects of process variation everywhere else in the circuit, but I cannot think of a way to reduce the variation in the subthreshold portion of the circuit. Gate area is maximized in accordance to Pelgrom's Law, and I cannot use adaptive body biasing as this is a fully depleted SOI process.
This is my first time working with subthreshold devices as well as process/mismatch sensitive devices, any tips on design methodology would be greatly appreciated.

give some more information about what you are trying to do and perhaps we can suggest alternative methods.