Hi,

I am trying to understand PN/jitter and evaluate which performance I need for my circuit but this seems rather intricate.

The "SNR degradation" due to jitter in a clock can be estimated with a well known formula of

20*log10(2*pi*fc*sigma)

Suppose I have a zero-IF architecture where the maximum LO frequency is 3 GHz and want not more than 55dB SNR degradation I would need a jitter of 100fs RMS. Isn't this a pretty tough value?

Now I may say this only applies to sampled systems (like an ADC) but I can do some math with a jittered LO (used for zero-IF downconversion) to arrive at the same result and I can verify this results with system-level MATLAB/Simulink simulations which confirm the first-order equation above.

Now I know about a system with exceptional performance (e.g. SFDR 83dB, noise floor/spurs <-80dBc resulting in an effective EVM of -60 dB). It is used as a receiver for digital predistortion, hence such high performance is required. However, the PLL which is used has the following phase noise:



The resulting integrated jitter is 744fs RMS and hence the expected EVM just due to this phase noise not more than 40dB (also from the above formula with their maximum frequency of 2170 MHz this is -39.87dB)

So I wonder: HOW DOES THAT WORK? I know that it is a het (not zero-IF) and looking at the resulting phase noise spectrum it can be seen that much of the effective added noise is very close to the carrier (from the picture: 1 MHz from the carrier, the noise is <-140dBc/Hz). Filtering out this part of the signal would increase the EVM tremendously (in my simulations, I can add a digital IIR highpass filter with Fstop=100, Fpass=10MHz and EVM increases to -70dB!)

Can I conclude that a zero-IF architecture is a desaster in terms of phase noise because the signal of interest goes all the way down to zero (in a similar way as 1/f noise and DC offsets)?


Thanks!!