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High speed cmos divider with large divide ratio (Read 1411 times)

msl New Member Offline Posts: 4	High speed cmos divider with large divide ratio Apr 06^th, 2016, 9:01am Hi, Does anyone here have experience of designing a say cmos0.13um divider with input signal at 2GHz and a divide ratio at 1-16,383? The input speed is too high to synthesize the divider using RTL codes. Thanks CC
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loose-electron

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Re: High speed cmos divider with large divide ratio
Reply #1 - Apr 7^th, 2016, 5:18pm

msl wrote on Apr 6^th, 2016, 9:01am:

Hi,

Does anyone here have experience of designing a say cmos0.13um divider with input signal at 2GHz and a divide ratio at 1-16,383? The input speed is too high to synthesize the divider using RTL codes.

Thanks

CC

You will end up doing an analog-centric design for a predivider, using current mode (aka ECL, PECL, current steering) logic, to get the divider down to something that can clock conventional CMOS logic, after a suitable level shifting circuit.

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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