msl wrote on Apr 6th, 2016, 9:01am:Hi,
Does anyone here have experience of designing a say cmos0.13um divider with input signal at 2GHz and a divide ratio at 1-16,383? The input speed is too high to synthesize the divider using RTL codes.
Thanks
CC
You will end up doing an analog-centric design for a predivider, using current mode (aka ECL, PECL, current steering) logic, to get the divider down to something that can clock conventional CMOS logic, after a suitable level shifting circuit.