The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 12:00pm
Pages: 1
Send Topic Print
HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN? (Read 2110 times)
binod23
New Member
*
Offline



Posts: 1

HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?
Apr 08th, 2016, 6:30am
 
Dear All,


     I want to record the states of all flipflops in the design as the verilog design is simulated for some fixed number of cycles. I don't have the need to view the  waveforms of those signals. I want to use those states for  further processing. Please tell how to dump the states of the flipflops corresponding to each simulation cycle ? I am ready to use any simulator --vcs/ncsim/modelsim/icarus verilog.

 I doubt if  the vcd file which is generated would serve my purpose as I don't know any method to open vcd files except gtkwave that I don't want (as waveforms are not needed).

Please help. It is urgent.

Thanks In Advance
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?
Reply #1 - Apr 21st, 2016, 12:51pm
 
This probably should have been posted in "AMS Simulators" instead.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.