Hi,
I'm using gm/id transistor sizing approach to design a low power opamp. I have a few questions regarding the same.
1) I biased the input transconductances in moderate inversion by choosing the gm/id of the differential transistors = 18, but while running dc simulation in cadence these transistors are shown to be biased in region 2 even though I get required gm. Is this correct? Will the transistors ever be in region 2 if they are in moderate inversion?

okk thanks.
while sizing the transistors in the folded cascode, I used Vov = 2*id/gm and found the sizes from the gm/id lookup table. Since I used worst case condition currents, the dc simulation shows these transistors to be biased in region 2 but gm/id = 18 (since the current is less than worst case current) which implies that these transistors are close to subthreshold under normal bias conditions. Will this be a problem as these transistors should biased in strong inversion?