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estimating 1/f corner frequency (Read 979 times)

JARVIS

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estimating 1/f corner frequency
Apr 10^th, 2016, 12:09am

Hi,
I am trying to estimate 1/f corner frequency by doing noise analysis in cadence ADE L of a circuit designed in 180nm UMC Technology. Even though I don't get any errors, the input referred noise plot(output noise/gain)shows the 1/f corner to be in the order of MHz which is clearly too high since I'm not using any high-frequency transistors. What am I doing wrong?

noise.jpg

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ULPAnalog Community Member Offline Posts: 97	Re: estimating 1/f corner frequency Reply #1 - Apr 10^th, 2016, 11:19am Hello It might be possible. Is the input device pmos or nmos? What are the dimensions and what the the bias current? Flicker noise corner depends on these factors.
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JARVIS New Member Offline Posts: 4	Re: estimating 1/f corner frequency Reply #2 - Apr 10^th, 2016, 12:20pm The circuit that I'm simulating is a basic Current feedback instrumentation amplifier .The input transconductances are biased in moderate inversion, and their sizes are around 50u/0.5u and tail bias currents are 28 uA. The circuit schematic is shown below
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ULPAnalog

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Re: estimating 1/f corner frequency
Reply #3 - Apr 10^th, 2016, 1:46pm

Ok. A few more things to consider. Is most of the flicker noise coming from the input pair or from the current sources M41/42 and M71/72.
In general 180nm is a pretty much mature process and is generally well characterized and from my past experience with 180nm process (from other foundry though) is that the noise sims match pretty well with silicon data.

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