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Two-Dimensional Arrays in Verilog-A (Read 48 times)
AA
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Two-Dimensional Arrays in Verilog-A
Apr 14th, 2016, 10:57am
 
Hi everyone!

I need a two dimensional array of real numbers in my analog model.
I googled, but unfortunately found nothing. The only related thing was
in the digital verilog domain when creating a register file. That does not
help in my case.

Anyway, I borrowed an idea from the compilers course, in which you
can simulate 2D arrays using 1D. However, this is kind of not neat,
and I wonder if there is a better way of doing it.

Any idea?

Thank you all.
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Geoffrey_Coram
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Re: Two-Dimensional Arrays in Verilog-A
Reply #1 - Apr 21st, 2016, 12:50pm
 
Did you check the Verilog-AMS Language Reference Manual?  I opened up the latest (version 2.4) and searched for "array" and immediately found "3.4.8 Multidimensional parameter array examples" in the table of contents.  And in section 3.2, there's this example:

real vtable[0:16][0:7][0:64]; // a multidimensional real array
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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