radioelectra
New Member
Offline
Posts: 1
|
Hi all,
In order to increase the capacitance density instead of using MOM, can we build decap with 1.8 volt tolerant MOS transistor?
The structure will be pmos transistor three terminals (source, drain, bulk) tied vcco and gate tied to vcco/2 where vcco/2 derived from resistive divider circuit.
What are the issues with above topology
|