Hi,

I am new to current mode regulation loop, pls help me in understanding these

1) how to estimate systematic error in ouput current(or voltage)  due to finite loopgain like an LDO ? (not sure even something like this exists here ...  as I have no clue how to model dc gain)

2) the negative feedback regulation loop sets the duty cycle needed for the output to reach the reference.
so here what is the impact of loop delay (component delays added up)  on the average output ?

if the delay is too large I would expect stability issues as it adds  excess phase to the loop.


Thanks,
yvkrishna