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Improving simulation speed with verilog-a blocks (Read 2425 times)
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Improving simulation speed with verilog-a blocks
Oct 03rd, 2016, 12:50am
            I am working on a mixed signal (high-speed io) design which requires precise measurements.Right now they are done using verilog-A blocks (there are handful of them) but the downside is the simulation speed has become drastically slow.
I observed that the simulation speed has become acceptable(50% less) without the verilog-a blocks.
I am using APS with multi-core.
Is there a way to improve speed with the existing setup itself or resort to something else like OCEAN.

If I use OCEAN for the same will I get considerable benefit ?

I understand that verilog-a can control the simulator for tight timesteps thereby giving good accuracy and I have to explicitly run with max timestep if I use ocean.
Let me know if I get anymore drawbacks on using ocean.

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Andrew Beckett
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Re: Improving simulation speed with verilog-a blocks
Reply #1 - Dec 29th, 2016, 11:04am
Huh? OCEAN is just a scripting language (a set of SKILL functions actually) to produce the netlist and post-process the results; in essence it performs the same task as ADE and is equivalent to ADE. It wouldn't affect the simulation time unless you'd picked simulation options that don't make sense.

It's quite likely that your models are suboptimal; you might want to try using the AHDL linter option, or the +diagnose switch on spectre which can help diagnose performance problems in transient simulations.

You might want to contact Cadence customer support at so that you can share more information and get more guidance as to how to address the problem you're seeing.


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