Hello All. I have a Veriloga code for phase unwrap block used in phase to voltage converter block that has been suggested in
http://delivery.acm.org/10.1145/1330000/1326256/p887-kim.pdf?ip=17.236.17.12&id=...The code is given below.
Code:`include "constants.vams"
`include "disciplines.vams"
module phase_unwrap(c,s,out);
input c,s;
output out;
voltage c,s,out;
parameter k=1e7;
real te,co,so;
analog begin
@(initial_step)
begin
te=0;
co=1;
so=0;
end
co=cos(V(out));
so=sin(V(out));
te=atan2(V(s)*co-V(c)*so,V(s)*so+V(c)*co);
V(out) <+ `M_PI*2*k*idt(te,`M_PI/4);
end
endmodule
There is an IQ demodulator block whose I and Q components are fed to the "c" and "s" inputs of the phase unwrap block. The phase unwrap block has an integrator block in it and an atan2 function which extracts the angle from the c and s inputs. Details of this block are given in the paper whose link I have pointed to above.
This block has a convergence issue. Unless I use "sigramp" option, this never converges. There are times when this cell works fine without "sigramp" option but then the output blows up.
I need your advice to somehow make this block more friendly towards convergence. I would greatly appreciate your help with this problem of mine.