The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 25th, 2024, 3:20pm
Pages: 1
Send Topic Print
Stacking of MOS to reduce random mismatch in a current mirror (Read 916 times)
vroy_92
Junior Member
**
Offline



Posts: 30
Leuven, Belgium
Stacking of MOS to reduce random mismatch in a current mirror
Nov 07th, 2016, 8:06pm
 
Why are identical MOSes used in a current mirror to reduce mismatch?
It is a common practice to stack devices to reduce random mismatch is a current mirror. The stacked devices behave like resistors, thus making the entire stacked structure behave like a source degenerated common source transistor. The effective gm reduces and thus current mismatch due to Vth mismatch comes down as well.
But it is not necessary to use the same width to get a MOS resistor which can effect source degeneration.
Back to top
 
 

Regards,
V Roy
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.