Hi all. I'm running Verilog-AMS simulations with ncvlog/ncelab/ncsim. I keep running into nasty bugs in my Verilog-AMS code because of undeclared pins. Is there a way to make ncvlog throw an error when it reaches an electrical that wasn't declared as such?
For example,
Code: electrical VDDINT;
electrical pin1, pin2;
analog VDDINT <+ 1.2;
my_spice_netlist xfoo( VDD, pin1, pin2);
Will compile and run, even though I never declared VDD. Obviously there's a typo here, but when my modules have hundreds of pins it gets hard to notice stuff like that. Even a warning message would be great.
A look through the documentation made me think I might try `default_discipline but it only seems to work for discrete natures.
Thanks!