Why don't you just simulate with different Fclks? The sims should take less than 5 mins. Pnoise sims are pretty fast. Transient noise sims are very slow.

In order to teach others, can you please post what you see?

I'll post what I've seen afterwards.

Regards,
Daniel Lam

For the pnoise sim, I basically run a jitter sim, integrate the jitter, and divide by a peak gain. I was running a 2-4 GHz clock. Each sim (PSS+Pnoise) took about max a minute. 10 sidebands, moderate tolerances.

For my comparator with different fclk (which means sidebands and integration limit changes). Also, the clock was a square pulse with the same rise/falltime of 5 ps:

100M : 210 uVrms (jitter 70m)
1G : 373 uVrms (jitter 124m)
2G: 376 uVrms (jitter 123m)

I had a difference, and I think it was due to the integrated jitter range (along with the comparator characteristics). I didn't look any deeper after that.

Ken,

Since the bandwidth of my circuit is about 1000X than the clock freq, I think atleast few thousand sidebands are needed in pnoise setup to take of folding effects.
(some people even suggest 10X the ratio of bw to clk frq which is 10,000 sidebands  )

This is the cause of slowness in my setup.

Let me know if I am missing something here.


Thanks,
Vamshi

Thanks for the suggestion about fullspectrum Andrew.

So this would be in a 2 step, first give only few (~100) sidebands to get a crude estimate for flicker noise corner at the output of the comaparator and then use that to get the correct estimate for sidebands in the next iterations (??)


Thanks,
yvkrishna

yvkrishna wrote on Mar 16^th, 2017, 8:22pm:


No, it's not in two steps. I didn't say that... it doesn't work the way you are suggesting.

Did you try it?

Andrew.