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PLL: Frequency step response, Lock range simulation (Read 3883 times)
deba
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PLL: Frequency step response, Lock range simulation
Mar 28th, 2017, 9:33am
 
Hi,

1) How does one check the PLL closed loop transient response to a step change in the input frequency? Is there a source available which models frequency step?

2) How does one simulate/measure the lock range for PLL?

Thanks
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Ken Kundert
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Re: PLL: Frequency step response, Lock range simulation
Reply #1 - Mar 28th, 2017, 12:13pm
 
Easy to create such a source with Verilog-A.

-Ken
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deba
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Re: PLL: Frequency step response, Lock range simulation
Reply #2 - Mar 31st, 2017, 12:34am
 
Hi Ken,

Thanks for the suggestion. I managed to do it using dynamic parameter option in transient analysis.

Thanks
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Hercules Poirot
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Re: PLL: Frequency step response, Lock range simulation
Reply #3 - Aug 8th, 2017, 6:03am
 
Make a small signal model of the PLL.
The steps to do it are as follows:
1. Your PFD [well in this small signal 'phase' model its just going to be a phase detector] can be just a voltage controlled current source. [VCCS from analogLib].
2. The current source value will be Icp / (2*pi)
3. You can make the loop filter using R & C (from analogLib)
4. Your VCO will be VCCS followed by a 1F capacitor [to emulate an integrator] with a gain of your Kvco (make sure its in rads/s-V).
5. Your divider can be just a VCVS with a gain of 1.0/feedback_factor.

The output of the divider and the reference input goes to the VCCS of (1).

To simulate the effect of a frequency step, just give a ramp input with a slope of fstep*2*pi [the 2*pi factor is to account for Hz to radians/s-V conversion]
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Hercules Poirot
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Re: PLL: Frequency step response, Lock range simulation
Reply #4 - Sep 8th, 2017, 9:42am
 
See this image. I use this to run AC analysis using Spectre.
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pll_analysis_schematic.png
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