Hercules Poirot
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Make a small signal model of the PLL. The steps to do it are as follows: 1. Your PFD [well in this small signal 'phase' model its just going to be a phase detector] can be just a voltage controlled current source. [VCCS from analogLib]. 2. The current source value will be Icp / (2*pi) 3. You can make the loop filter using R & C (from analogLib) 4. Your VCO will be VCCS followed by a 1F capacitor [to emulate an integrator] with a gain of your Kvco (make sure its in rads/s-V). 5. Your divider can be just a VCVS with a gain of 1.0/feedback_factor.
The output of the divider and the reference input goes to the VCCS of (1).
To simulate the effect of a frequency step, just give a ramp input with a slope of fstep*2*pi [the 2*pi factor is to account for Hz to radians/s-V conversion]
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