Hello all,
I have a question on designing using gm/Id. So I've successfully designed a CS Amp with resistive and PMOS active load and now I'm currently trying to design CS Amp with Current Mirror Load in 130nm using gm/Id technique. Shout out to ULPAnalog for introducing me to this technique!
Although this technique worked perfectly when designing with resistive and pmos load, the gain and output voltage was not as expected when using current mirror load. I suspect it has something to do with the output voltage or the DC operating point.
Here's what I've done:-
1)Characterized NMOS with Vdrain =0.6V, Vsource =0V , Vgate is swept from 0 to 1.2V.
The gm/Id, Id/W and gm/gds is plotted with respect to Vgs.
2)Characterized PMOS with Vdrain = 0.6V, Vsource =1.2V , Vgate is swept from 0 to 1.2V.
The gm/Id, Id/W and gm/gds is plotted with respect to Vgs.
3)Gain equation of this architecture is given by (gm of nmos)/gds,nmos+gds,pmos
4)Chose gm to be 3.14mS, assuming the desired BW is 100MHz with load capacitance of 5pF. (I didn't simulate with the cap since my focus is the gain rather than BW don't think this matters tho).
4)DEvice dimensions
NMOS = 99um/1.5um PMOS = 60um/1um Current = 278uA.
5)Calculated gain should be around 277V/V but the simulated gain was around 2V/V.
6)As far as the The DC operating point of the transistors, only the DC current matches the calculation. The gm of devices as well as drain voltages of the device do not match/not as expected.
7)NMOS was biased at 450mV.
9)I have attached the schematic as well as the transistor characterization plots, if it helps.
Questions:-
1)What did I do wrong or what can I change? I can't for the life of me figure it out. I did do a DC analysis using the sizing mentioned above and at the point I biased my NMOS I should have gotten close to 0.6V instead of 0.996V which is causing my PMOS to be in linear instead of saturation region.
2)Is it normal for it to have a large size? What is the typical sizing of an op amp? Does the PMOS or NMOS reach more than 100um in any case? I'm used to designing digital standard cells (which are relatively smaller) and the large size of the op amp transistor is scaring me a bit to the point where I have doubts about my design lol.
3)I suspect there is a tradeoff here between output voltage/swing and gain but I can't quite figure it out. I characterized my transistors such that the output voltage would be half of the Vdd (1.2V) for higher voltage swing. Should I re-characterize my transistors?
Any and all help is greatly appreciated and thanks in advance!
Edit: This thing won't let me attach multiple pics, will post the plots later.